Design optimization is an important component of design using electronic design automation (EDA) tools. The design optimization process helps optimize various characteristics of the design, such as speed of operation, power usage etc. Timing analysis, optimization and closure is one of the needed optimizations. Timing optimization is a very time consuming and iterative process that evaluates the performance of each gate used in a design, to ensure that the delay through the gate with the fan-in and fan-out loading is optimum. This process requires the gate to be modeled with and without buffering or by addition of multiple levels of inverters that enable the gate to function with the optimum rise and fall times for the switching signals, while providing an optimum delay through the integrated gate.
The existing timing optimization processes are iterative in nature and run various buffering and sizing transforms to converge to a final optimized delay values (DV) for the gate. The delay values comprise at least the gate delay and rise and fall times, for each loaded gate. The DV can also be represented by a slack value or slack number which are used interchangeably to specify the same set of gate characteristics. FIG. 1 show block diagrams of gate configurations 110, 120 and 130 that are used in a design to achieve speed and need to be analyzed to achieve the optimum DV for various gate loads. The gate configuration 110 shows a gate 101 with a load 105 and no buffering, gate configuration 120 shows a gate 101 that includes a buffer tree 121 of one or more buffers, as part of the gate configuration 120 to increase the gate drive to load 105, and gate configuration 130 shows a gate 101 with multiple inverters 131 and 132 that form a part of the gate configuration 130 providing drive to the load 105. The load 105 can comprise connected load from one or more driven gates. The static timing analysis (STA) timing analysis is used to arrive at the best gate configuration and sizes of the gate 101, the buffer 121 and inverters 131 and 132 to be used, to achieve the optimum delay performance of the configured gate. This is done by an iterative process for all the gates in the critical path of a design at least, if not for all the gates of the design from a starting configuration and sizing provided mainly based on the designers experience and intuition. Hence this is a very time consuming and resource intensive process.
FIG. 2 is a block diagram 200 showing the prior art system for implementation of the iterative process of STA for achieving the timing optimization. Each incremental change of buffer or sizing of the gate configuration components require the extraction of a new net-list and a new incremental STA run to arrive at the new DV for the gate. The flowchart 200 for the process operates as described herein below:
The design net-list is input into the EDA system for STA for design timing optimization (DTO). S201.
The initial STA is conducted on the design with the design net-list provided. S202.
The result for the initial gate configuration and initial values of DV, for each gate in the design are extracted. S203.
For each gate the extracted initial run values, the sizes, the associated gate configurations and net-list are stored in a database S220.
For the first gate to be optimized the initial values are loaded into the timing optimization system (TOS), which is typically an EDA system, from the database. S204.
The buffering and sizing changes are made by adding a buffer or inverter or increasing the sizes of devices to improve drive. The incremental changes are made based on the initial sizing and buffering of the gates done intuitively by the designer. S205.
A design net-list is generated for the design with the new gate configuration including new buffering and sizing. S206.
An incremental STA is run to assess the impact of the gate configuration changes. S207.
The DV for the gate are calculated from the result of the run. S208.
The resulting DV is compared with the stored DV for the gate. S209.
If the resulting DV is better than the stored DV, the gate related information in the database is updated with the new gate information comprising the new gate configuration, and associated DV. The gate optimization process is repeated from step S205 by changing the buffering and sizing of the gate configuration and extraction of net-list. S210.
If the result, of iteration, is not better indicating that the gate is closer to optimization, the two gate configurations are checked to see if the gate configuration in the database is checked for all types of buffering configurations allowed. S211. If not then the optimization process is repeated from step S205 by changing the buffering and sizing of the gate configuration until all configuration types are checked.
If the gate timing is optimized then the gate is checked to see if it is the last gate to be timing optimized. S212.
If it is not, then the system is instructed to load the next gate configuration (net-list) from the database and continue the optimization process from step S204, for the next gate to be timing optimized. S213
If the gate is the last gate to be optimized, the gate optimization process is complete with the optimized gate configuration net-list and DV for all gate configurations stored in the database. The full design STA is done with the gate net-list replaced in the design to optimize the design with actual fan-outs and loads and the DTO is stopped. S214.
As is clear from the flowchart 200 description for DTO, there are a large number of iterative steps which are time consuming and are resource intensive, such as net-list generation and running the incremental STA to generate the gate delay and the signal rise and fall times for each gate in the design. Typically the optimization process takes over 10 to 20 iterations for each gate to achieve convergence Fig. to S205 to S211, since all the buffering and sizing has to be done incrementally from the original value to get to the optimized values. A person of ordinary skill in the art would readily appreciate that as the scale of integrated circuits (ICs) increases in number, i.e., hundreds of millions of gates realized, the number of iterations grows at least linearly. It will be therefore advantageous if a method can be realized that reduces the number of iterations with the time taken and uses less EDA resources to achieve DTO.